发明名称 Edge termination for silicon power devices
摘要 A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer. A well region of a second, opposite conduction type is formed at the upper surface of the upper layer adjacent the edge termination zone, and an oxide layer is formed over the upper layer and edge termination zone.
申请公布号 US6534347(B2) 申请公布日期 2003.03.18
申请号 US20010792345 申请日期 2001.02.23
申请人 INTERSIL CORPORATION 发明人 ZENG JUN;DOLRY GARY MARK;MURALEEDHARAN PRAVEEN
分类号 H01L29/78;H01L21/04;H01L21/336;H01L29/06;H01L29/12;H01L29/24;H01L29/267;(IPC1-7):H01L21/332 主分类号 H01L29/78
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