| 摘要 |
An automated method of analyzing crosstalk in a digital logic integrated circuit, the method operating on a digital computer, is described. The method uses available software to make an extracted, parameterized netlist from a layout of the integrated circuit. For at least one potential victim wire of the plurality of wires, determining a subset of the wires of the chip are found to be potential aggressor wires that may couple to the victim wire. The aggressor wires are combined into a common aggressor. A risetime of the common aggressor is calculated and used to calculate the magnitude of coupled noise on the victim wire induced by the aggressor wires. An alarm threshold for each potential victim wire is determined based upon the type of logic gate that receives the victim wire. The alarm thresholds for each potential victim wire are compared to the calculated height of a coupled noise on the victim wire to determine which, if any, wires of the design suffer enough crosstalk noise that they should be redesigned.
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