| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory system which enables efficient defect relief. SOLUTION: After a CPU 102 writes data to a memory cell in a memory cell array 103, the data are read and verified and when the data are discrepant, the CPU supplies a phase program signal FP to a phase program part 109, which programs a defective address in a phase part and substitutes a spare memory for the memory cell where the defect occurs according to the address programmed in the phase part. A data path from a defect DQ line to a corresponding DQ buffer is switched to a data path to the DQ buffer from the spare DQ line and the memory cell where the defect occurs is replaced with the spare memory, so that even if the memory cell becomes defective owing to secular change after the memory cells are built in the system, the memory cell can be relieved without causing the system itself to become defective.
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