发明名称 DATA TRANSFER SYSTEM BETWEEN MEMORIES OF DSPS
摘要 PROBLEM TO BE SOLVED: To provide a data transfer system between the memories of DSPs which can transfer data between the memories in a plurality of DSPs with a circuit of a simple configuration in a device having the plurality of DSPs (digital signal processors). SOLUTION: The device having a CPU and a plurality of DSPs is constituted of a transfer request selection circuit for receiving the transfer request signal from the CPU or the DSPs, a transfer request maintaining circuit which receives and maintains the transfer request signal, and transmits the instruction signal for performing the data transfer according to the priority order of the transfer request signals, an expansion bus control circuit which is connected to each DSP via an expansion bus, receives the instruction signal, reads the transfer information of the CPU or the DSPs, and performs the data transfer according to the transfer information, and a DPRAM which maintains the transfer data for the CPU while the expansion bus control circuit reads/writes the transfer data.
申请公布号 JP2003076654(A) 申请公布日期 2003.03.14
申请号 JP20010269313 申请日期 2001.09.05
申请人 NEC CORP 发明人 NAKANO MOTOO
分类号 G06F15/177;G06F13/28;G06F13/38;(IPC1-7):G06F13/28 主分类号 G06F15/177
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