| 摘要 |
PROBLEM TO BE SOLVED: To provide a pulse generating circuit for acceleration/constant-driving a pulse motor in which excellent follow-up performance is exhibited in acceleration through relatively simple circuitry. SOLUTION: In the circuitry shown on Fig. 2, a reference clock F, an adder 1, a counter 2 and a second counter 5 are employed. The adder 1 adds it output (ALSB-AMSB) and the output (BLSB-BMSB) of the counter 2 at the reference clock F and when the output from the adder 1 reaches a most significant bit (AMSB), addition is stopped by a most significant bit determination signal Lout1 and the second counter 5 begins to count the reference clock F. When the second counter 5 reaches an upper limit, an output pulse Fout is inverted by an upper limit value determination signal Lout6. Every time when the output pulse Fout is inverted, the adder 1 and the second counter 5 are cleared in synchronism with the reference clock F and then the adder 1 begins addition and the second counter 5 stops counting. The counter 2 has an initial value (CLSB-SMSB) of natural number and performs counting once in synchronism with the reference clock F every time when the output pulse Fout is inverted twice and stops counting when an upper limit value is reached. |
