发明名称 METHOD FOR LAYOUT
摘要 PROBLEM TO BE SOLVED: To prevent breakdown of an element due to antenna effect without lowering the mounting efficiency of transistor. SOLUTION: If the length of a signal line to the area of the gate of an input stage transistor in a second circuit exceeds a specified allowable value (S14), the signal line is detoured up to the uppermost layer thereof at a position in the range of the allowable value the signal line (S16) thus blocking charges due to antenna effect until the detouring part is formed. The uppermost layer of the signal line is formed simultaneously upon formation of the detouring part and charges stored in the signal line are discharged to the first circuit side. Mounting efficiency of transistor is prevented from lowering by eliminating a protective diode for preventing breakdown of an element.
申请公布号 JP2003078012(A) 申请公布日期 2003.03.14
申请号 JP20010265309 申请日期 2001.09.03
申请人 HITACHI LTD 发明人 AIDA SHINYO
分类号 G06F17/50;H01L21/82;H01L21/822;H01L27/04;H01L27/118;(IPC1-7):H01L21/82 主分类号 G06F17/50
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