发明名称 |
METHOD FOR CIRCUIT SIMULATION |
摘要 |
PROBLEM TO BE SOLVED: To simulate in a short time and with accuracy by a transistor size reflecting variations in a manufacturing process. SOLUTION: In a model for circuit simulation, a model parameter with a rage of usefulness of the transistor size, parameters for correction 1 representing an amount of change of the transistor size due to the variations in the manufacturing process and a range of an n-type MOS transistor are divided into two ranges, and a first model parameter set 3 used for a range of usefulness 2 of a first transistor and a second model parameter set 5 used for a range of usefulness 4 of a second transistor size are described. The ranges of usefulness 2 and 4 are organized in such a manner as to automatically change the transistor size by setting the amount of change in a manufactured transistor size against a designed value to the parameters for correction 1.
|
申请公布号 |
JP2003076737(A) |
申请公布日期 |
2003.03.14 |
申请号 |
JP20010265534 |
申请日期 |
2001.09.03 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
NAKADA KAZUHISA;SAWARA YASUYUKI |
分类号 |
G06F17/50;H01L21/82;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|