| 摘要 |
PROBLEM TO BE SOLVED: To provide a design method for semiconductor integrated circuit capable of reducing in an area of a semiconductor integrated circuit by extracting logic information from circuit connecting information and mapping a block with the smallest area to the logic information. SOLUTION: In the design method, in a step S15, logical groups are created at every sequential circuit by originating from an output terminal of a sequential circuit included in the semiconductor integrated circuit, in a step S16, the logic information at every logical path is extracted, in a step S17, the logic information with area information corresponding to the logic information at every logical path is extracted and the block with the smallest area is selected among the logic information, in a step S110, the circuit connecting information is created by using the block and in a step S111, an automatic layout is performed by using the circuit connecting information.
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