| 摘要 |
PROBLEM TO BE SOLVED: To provide an integrated circuit that can suppress parasitic leak current accompanied with no increase in chip size and prevent the reduction of withstand voltage. SOLUTION: An n-well area 12 is formed shallow at a slit 14 in the surface layer of a p<-> substrate, and separated p<-> offset areas 13a and 13b are formed, so that no cavity of a depletion layer is produced at the slit 14 and the reduction of withstand voltage can be prevented. In addition, the formation of the slit 14 can suppress parasitic leak current, and the increasing of parasitic resistance can reduce the size of chip.
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