发明名称 GATE ESTIMATION PROCESS AND METHOD
摘要 A method comprising maintaining a circuit design parameter file for a circuit being designed by a circuit designer. The circuit design parameter file specifies a physical characteristic of the circuit. The method monitors a design environment to detect the addition of a circuitry component to the circuit and access a component design parameter file that specifies at least one design parameter for that added circuitry component. The method updates the circuit design parameter file based on the at least one design parameter included in the component design parameter file.
申请公布号 WO03021496(A2) 申请公布日期 2003.03.13
申请号 WO2002US27009 申请日期 2002.08.23
申请人 INTEL CORPORATION (A DELAWARE CORPORATION) 发明人 WHEELER, WILLIAM;ADILETTA, MATTHEW
分类号 G06F17/50 主分类号 G06F17/50
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