| 摘要 |
The present invention relates to systems for communicating with synchronous devices, in particular, to automatic test equipment (ATE) for memory device testing and, more specifically, to a test system for testing a high-speed synchronous memory device using DQS signals obtained from the memory device to achieve the precise fault strobe timing characteristics. The test system for testing a memory device comprises a synchronisation unit for triggering fault strobe generators with respect to DQS signals from the memory device under test. The synchronisation unit comprises a plurality of delay generators, e.g. verniers, for providing a controlled delay for DQS signals from the memory device and additionally a plurality of delay elements for delaying DQ data from the memory device to provide the possibility to setup negative timing delay intervals for fault strobe with respect to received DQS signals. The invention is particularly appropriate for testing memory devices having reference signal for data receiver synchronisation, such as DDR Synchronous Dynamic Random Access Memory (DDR SDRAM), DDR SGRAM (Synchronous Graphics Random Access Memory), DDR II SDRAM, QDR SRAM, etc. |
