| 摘要 |
A process for economical and efficient fabrication of gate electrodes no larger than 50 nm, which is beyond the limit of exposure, is characterized by gate-electrode trimming and mask trimming with high resist selectivity which are performed in combination. The process is also preferably characterized by performing trimming and drying cleaning in a vacuum environment and may also include steps of inspecting dimensions and contamination in a vacuum environment. The process can be implemented to provide the effects of forming a gate no longer than 50 nm (beyond the limit of exposure) without restrictions on the resist thickness; reducing contamination resulting from transfer of wafers from one step to next, thereby improving yields; preventing resist from hydrolysis by ArF laser, thereby reducing roughening which adversely affects the gate width; and ensuring stable yields despite variation in dimensions and contamination owing to the additional dry cleaning step and feed-forward control based on CD inspection and contamination inspection.
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