发明名称 |
Modifying a hierarchical representation of a circuit to process features created by interactions between cells |
摘要 |
One embodiment of the invention provides a system for analyzing a layout related to a circuit on a semiconductor chip. The system operates by receiving a design hierarchy specifying the layout of the circuit. This layout includes a set of hierarchically organized nodes, wherein a given node specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes located under the given node in the design hierarchy. The system operates by modifying the design hierarchy by examining a set of sibling nodes that are located under a parent node in the design hierarchy in order to identify a set of interacting geometrical features between the set of sibling nodes. Next, the system then moves the set of interacting geometrical features to a new child node under the parent node, and then performs an analysis on the modified design hierarchy.
|
申请公布号 |
US2003049550(A1) |
申请公布日期 |
2003.03.13 |
申请号 |
US20010952896 |
申请日期 |
2001.09.10 |
申请人 |
NUMERICAL TECHNOLOGIES, INC. |
发明人 |
MANOO MASOUD |
分类号 |
G06F17/50;(IPC1-7):G03C5/00 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|