发明名称 |
SIMULATING A LOGIC DESIGN |
摘要 |
Simulating a logic design comprised of combinatorial logic and state logic includes representing the combinatorial logic and the state logic using separate graphic elements and associating computer code that simulates portions of the logic design with a graphic element that represents the combinatorial logic and with a graphic element that represents the state logic. |
申请公布号 |
WO03021492(A2) |
申请公布日期 |
2003.03.13 |
申请号 |
WO2002US26852 |
申请日期 |
2002.08.23 |
申请人 |
INTEL CORPORATION |
发明人 |
WHEELER, WILLIAM;ADILETTA, MATTHEW |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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