发明名称 ARCHITECTURE FOR INTERMEDIATE FREQUENCY DECODER
摘要 A decoder. The decoder includes interpolation circuitry that receives the digital signal and interpolates the digital signal to produce an interpolated digital signal. Additionally, the decoder includes a D/A converter that is coupled to the interpolation circuitry. The D/A converter receives the interpolated digital signal and converts such a signal to an analog signal. The decoder also includes an analog mixer coupled to the D/A converter. The analog mixer receives the analog signal and upconverts the analog signal.
申请公布号 WO0165680(A3) 申请公布日期 2003.03.13
申请号 WO2001US40238 申请日期 2001.03.02
申请人 ADC TELECOMMUNICATIONS, INC. 发明人 PAINCHAUD, DEAN;WACHTER, LAWRENCE, J.
分类号 H03D7/16;H03D9/00;(IPC1-7):H03D7/00 主分类号 H03D7/16
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