Logical circuit delay optimization system

摘要

A logical circuit is configured by connecting a plurality of circuit blocks. A driving ability value computation unit computes a driving ability value required for a target circuit block based on a delay rate of the circuit block indicating a rate of delay of a signal traveling in the circuit block by a load capacity value provided by the circuit block, a driving ability value of a prior stage circuit block prior to the target circuit block, and a load capacity value provided for the target circuit block. A change unit changes the specification of the device used in the target circuit block based on the driving ability value obtained by the driving ability value computation unit.