| 摘要 |
1,249,925. Integrated circuits. TEXAS INSTRUMENTS Inc. 19 March, 1969 [25 June, 1968], No. 14377/69. Heading H1K. After a first pattern of metallisation has been formed over an insulating layer on an integrated circuit wafer, a pattern of metallisation comprising testing pads is formed on a superposed insulating layer and makes connection to the first pattern. Electrical tests are then carried out to identify components up to specification and these are suitably interconnected by further metallisation. Typically a memory system consisting of four sections each containing sixty sixteen-bit words, part only of which is shown in Figs. 1 and 7, is built up in this way. Initially rows of transistors 12a-12p, 14a-14p and 16a -16p and word driver circuits 13-17 are formed by epitaxial and/or diffusion processes in a silicon wafer. An oxide passivating layer is then photo-etched and aluminium deposited thereon and pattern etched to connect the transistors as shown. Next a further oxide layer is deposited and apertured and an overall deposit of aluminium pattern-etched to provide testing pads electrically connected to points on the first level of interconnections, together with bus bars 69. An automatic 3-point probe is then indexed over the wafer to sequentially test the transistors for ability to represent a logic 1 and for leakage etc. The test results are stored on magnetic tape which is then fed to a computer which produces a slice map and computes therefrom in digital form an appropriate interconnection pattern for the required circuit. This is converted to analogue form and fed to the deflection plates of a CRT the display of which is photographed to form a discretionary interconnection mask. Then aluminium is deposited over the slice, a photoresist pattern formed with the aid of the mask and etching effected to form the interconnections, some of which, 86, 88 etc. are shown in Fig. 7. After further testing the device is packaged and re-tested. In the described arrangement the memory elements are single bipolar transistors junction isolated in an epitaxial silicon layer but different semiconductor materials and methods of isolation and testing can be used as can more complicated memory elements comprising resistors, capacitors, JUGFET's, IGFET's and TFT's. |
