发明名称 |
INTEGRATED CIRCUIT CHIP DESIGN |
摘要 |
<p>Methods for improving the design of integrated circuits by using layout tools, synthesis, and timing analysis to avoid getting stuck with spending to much time on premature optimizations (figures 2-13). As a design closes in a tapeout, several issues must converge simultaneously, and a useful concept is to increment relax added margins towards the desired target goals.</p> |
申请公布号 |
WO03021499(A1) |
申请公布日期 |
2003.03.13 |
申请号 |
WO2002US27921 |
申请日期 |
2002.08.29 |
申请人 |
MORPHICS TECHNOLOGY INC. |
发明人 |
WILLIAMS, TED, E.;FERRO, JONATHAN;TOVEY, DEFOREST;TSENG, LOUIS |
分类号 |
G06F17/50;H01L21/82;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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