| 摘要 |
A multiple matchline sense circuit for detecting a single, more than one, or no match conditions during a search-and-compare operation of a content addressable memory is disclosed. The circuit compares fife rising voltage rate of a multiple matchline to the rising voltage rate of a reference multiple matchline in order to generate a multibit result representing one of the three conditions. The circuit generates a self-timed control signal to end the search and-compare operation, and to set the circuit to a precharge state. |
