发明名称 |
Redundant information processing system |
摘要 |
An information processing system (100) having a plurality of modules (120,130) for synchronously executing the same instruction, comprising: a comparator (140) for comparing internal signals of said plurality of modules, and delivering an output signal representative of truth if there is a coincidence between the internal signals of said plurality of modules and an output signal representative of false if there is no coincidence; and a logical AND circuit (42) for receiving an output signal from said comparator and outputs from said plurality of modules, wherein an output of said logical AND circuit is used as an output of the system. <IMAGE>
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申请公布号 |
EP1291740(A2) |
申请公布日期 |
2003.03.12 |
申请号 |
EP20020014725 |
申请日期 |
1997.10.27 |
申请人 |
HITACHI, LTD. |
发明人 |
KANEKAWA, NOBUYASU;YAMAGUCHI, SHINICHIRO;MIYAZAKI, NAOTO;KASUYA, NAOHIRO;KAJIGAYA, KAZUHIKO;MIYAZAKI, YOSHIHIRO |
分类号 |
G05B9/03;G06F11/00;G06F11/16;G06F11/18;(IPC1-7):G06F11/18 |
主分类号 |
G05B9/03 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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