| 摘要 |
A programmable single-chip device, comprising a programmable gate array (PGA) section, a DSP core and a RISC core. The device is ideal for prototyping and deploying low-to-moderate volume implementations of high-bandwidth algorithms, which have processing requirements split between front-end, high iteration, low-numeric-agility, "wide" loadings, middle-end, moderate iteration, high-numerical-precision loadings and back-end, low-iteration, highly conditional loadings, without the commensurate problems inherent in the custom ASIC, joint FPGA/DSP/RISC (or even direct compilation to FPGA) solutions. |
