发明名称 Barrier metal integrity testing using a dual level line to line leakage testing pattern and partial CMP
摘要 A structure and method for determining barrier layer integrity for multi-level copper metallization structures in integrated circuit manufacturing. Novel testing structures prevent any conducting residues of the copper CMP from diffusing into the dielectric layer. Barrier layer integrity is tested by performing leakage or other electrical measurements between copper features on two different metal levels.
申请公布号 US6531777(B1) 申请公布日期 2003.03.11
申请号 US20000599839 申请日期 2000.06.22
申请人 ADVANCED MICRO DEVICES, INC. 发明人 WOO CHRISTY MEI-CHU;MARATHE AMIT P.
分类号 H01L21/66;H01L21/768;H01L23/544;(IPC1-7):H01L23/48 主分类号 H01L21/66
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