| 摘要 |
The subject of the present invention is to keep the wiring resistance low and reduce the variation of the wiring resistance in one identical lot in semiconductor devices of a multi level interconnect structure in which at least the lower wiring layer is an aluminum wiring layer.Contact holes (31, 51) are formed in dielectric interlayers (3, 5) of upper and lower wiring layers (1, 2, 4) by dry etching. In the method of forming the contact holes of the invention, the dry etching was applied in two steps divisionally. The first step of etching is applied with supplying CF4, CHF3, Ar and N2 into an etching chamber. The second step of etching is conducted with supplying CF4, CHF3 and Ar into the etching gas chamber.
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