发明名称 Controlling time delay
摘要 Controlling time delay includes using a delay line and a digital to analog converter configured to provide a signal to the delay line and including digital inputs configured to control the delay through the delay line by controlling amplifier gain elements included in the digital to analog converter.
申请公布号 US6531974(B1) 申请公布日期 2003.03.11
申请号 US20000545235 申请日期 2000.04.07
申请人 INTEL CORPORATION 发明人 CALLAHAN KENT R.;WONG KENG L.
分类号 H03K5/00;H03K5/13;H03L7/099;(IPC1-7):H03M1/66 主分类号 H03K5/00
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