| 摘要 |
A method and system for locating possible error or fault sites in a circuit or system. A set of nodes are chosen, using error models in some embodiments. By applying X values to the set of nodes in conjunction with three valued logic simulation output responses between the circuit and the specification are determined. Based on the comparison of the output responses between the circuit and the specification, an error probability can be assigned to the set of nodes. A ranked set of nodes is thereby produced with the highest ranked set of nodes being the most likely error or fault site.Furthermore, by determining the relationship of the inputs to the set of nodes to the outputs of the set of nodes in conjunction with test vectors and output responses determined in the specification, an error probability can also be assigned to the set of nodes. Use of symbolic logic variables can assist in determining the relationship of the inputs to the set of nodes to the outputs of the set of nodes. |
