| 摘要 |
A semiconductor package is proposed, in which a substrate is formed with a chip bonding area and a plurality of bond fingers surrounding the chip bonding area, and a plurality of bridging elements are disposed in a stagger manner between the chip bonding area and the bond fingers on the substrate. Multiple wire bonding processes are performed to bond first gold wires between the chip and the bridging elements, and bond second gold wires between the bridging elements and the bond fingers. This therefore significantly shortens a wire bonding distance as compared with only one time of wire bonding for electrically connecting the chip to the substrate. As a result, wire bond operability is improved, and the shortened wire bonding distance reduces wire length so as to enhance resistance of the gold wires to mold flow impact during molding, thereby preventing wire sweeping or wire sagging from occurrence.
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