Apparatus for associating cache memories with processors within a multiprocessor data processing system

摘要

An apparatus for associating cache memories with processors within a multiprocessor data processing system is disclosed. The multiprocessor data processing system includes multiple processing units and multiple cache memories. Each of the cache memories includes a cache memory controller, and each cache memory controller includes a mode register. Each mode register has multiple processing unit fields, and each of the processing unit fields is associated with one of the processing units for indicating whether or not data from an associated processing unit should be cached by a cache memory associated to a corresponding cache memory controller.