Encoder for multiplexing blocks of error protected bits with blocks of unprotected bits

摘要

An error detection encoder comprises separation circuitry for separating an input signal into a first sequence of error protected bits and a second sequence of error unprotected bits. Calculation circuitry produces an error check sequence from the first sequence and concatenates the error check sequence to the first sequence to produce a third sequence. The second sequence may be further separated into a first sub-sequence of higher significant bits and a second sub-sequence of lower significant bits. A multiplexer is provided for segmenting the third sequence into a plurality of first blocks and segmenting the first sub-sequence into a plurality of second blocks corresponding to the first blocks and multiplexing each of the first blocks with a corresponding one of the second blocks to produce a fourth sequence in which the first and the second blocks are arranged in an alternating order. The second sub-sequence is concatenated to the fourth sequence to produce an output sequence for transmission.