发明名称 |
Data management for multi-bit-per-cell memories |
摘要 |
A multi-bit-per-cell memory reduces the effect of defects and data errors by scrambling data bits before writing data. The scrambling prevents storage of consecutive bits in the same memory cell. When a memory cell is defective or produces an error, the bits read from the memory cell do not create consecutive bit errors that would be noticeable or uncorrectable. An error or a defect in a multi-bit memory cell causes at most scattered bit errors. Scramblers in multi-bit-per-cell memories can include 1) hardwired lines crossing between an input port and an output port, 2) programmable wiring options, 3) a linear buffer where reads from the buffer use addresses with swapped bits, or 4) a buffer array that switches between incrementing a row address first and incrementing a column address first when accessing memory cells in the buffer array.
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申请公布号 |
US6532556(B1) |
申请公布日期 |
2003.03.11 |
申请号 |
US20000492949 |
申请日期 |
2000.01.27 |
申请人 |
MULTI LEVEL MEMORY TECHNOLOGY |
发明人 |
WONG SAU CHING;SO HOCK CHUEN |
分类号 |
G06F12/14;G11C11/56;(IPC1-7):G11C29/00;G01R31/28;G06F12/04 |
主分类号 |
G06F12/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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