| 摘要 |
PROBLEM TO BE SOLVED: To ensure the stability of locking of a PLL even when a high processing speed is adopted for the phase comparator. SOLUTION: An EFM signal is frequency-divided by a 1/2 frequency divider 10 and its output signal S4 is inputted to a 1st stage data terminal D of a shift register 11 composed of four D flip-flop circuits 111-114, a clock signal CKP from a VCO 1 is inputted to a 1st stage clock terminal CK and an inverse of a clock signal PCK is fed to clock terminals CK of the 2nd and succeeding stages of the shift register 11. Furthermore, a 2nd stage output signal of the shift register 11 and an output signal S4 of a 1/2 frequency divider 10 are inputted to an EX-NOR gate 13, a 3rd and a 4th stage output signal Q3, Q4 of the shift register 11 are given to an EX-NOR gate 14 and output signals S5, S6 of the EX-NOR gate 13 and the EX-OR gate 14 are inputted to a post-stage charge pump 3. |
