| 摘要 |
PURPOSE: A system and a method for measuring a boundary scan test chip delay are provided to reduce the influence of a delay on a transmission line by measuring a signal delay of a pattern signal passing through a chip in a main controller to compensate the same. CONSTITUTION: A high speed clock generates a high speed clock signal. A counter(21) counts the high speed clock signal. A comparing unit(22) compares whether or not a pattern signal passing through a BSC(Boundary Scan Test) chip and the outputted pattern signal are equal. When they are equal, an adder-subtracter(23) calculates the delay which is generated when a signal passes through the BSC chip according to a number counted in the counter(21). A clock signal compensating unit(24) compensates a clock signal of a main controller according to the delay calculated in the adder-subtracter(23).
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