| 摘要 |
PURPOSE: To provide a semiconductor memory in which the memory capacity is increased while preventing increase of the cell area in the memory cells in a shadow RAM provided with ferroelectric capacitors in an RAM. CONSTITUTION: The memory cells in a shadow RAM have multilayer wiring layers 101-106 formed on a semiconductor substrate and, in the layout of a gate electrode 124, a word line 125, a power supply line, a GND line 130, a bit line 136, and lines 127, 132, 134 and 137 wiring the overlying and underlying wiring layers constituting the multilayer wiring layers, all lines except the wiring lines have the substantially same layout as that of the corresponding lines of the memory cells in an SRAM provided with no ferroelectric capacitor. Lines for wiring the overlying wiring layer and the underlying wiring layer are formed in an arbitrary pattern in the wiring layer increased as compared with that of a conventional shadow RAM and a structure for connection with the underlying wiring layer and a structure for connection with the overlying wiring layer are set at arbitrary different positions.
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