| 摘要 |
PURPOSE: A design for a GF(2¬16) serial multiplier using a GF(2¬4) infinite field is provided to reduce delay to obtain result, and to realize the serial multiplier with hardwares less than a parallel multiplier by designing the serial multiplier of the GF(2¬16) finite field with the use of a serial operator on a subfield. CONSTITUTION: In case that an order of the GF(2¬m) is consisted of the multiplication of two numbers larger than one, the GF(2¬m) has the subfields of GF(2¬u) and GF(2¬v). The serial multiplier on the GF(2¬m) finite field is realized by using the serial operators on the subfields. Thus, the serial multiplier is realized by three 16-bit registers, 64 2-input AND gates and 89 2-input XOR gates, and the result is obtained by four-clock time.
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