| 摘要 |
PURPOSE: A method for forming a transistor in a semiconductor device is provided to be capable of reducing channel length and improving processing margin by using an upper and lower gate electrode. CONSTITUTION: After forming a gate insulating pattern(22) on a semiconductor substrate(21), a lower gate electrode(24) having thin thickness and narrow channel length is formed on the gate insulating pattern(22). After forming an LDD(Lightly Doped Drain) region(27) in the substrate, an insulating spacer(29) is formed at both sidewalls of the lower gate electrode and the gate insulating pattern. An upper gate electrode(34) is formed on the lower gate electrode(24). At this time, the upper gate electrode(34) has a relatively thick thickness and wider channel length compared to the lower gate electrode(24).
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