VBB/VPP BIAS ARRANGEMENT METHOD OF SEMICONDUCTOR MEMORY

摘要

PURPOSE: A vbb/vpp bias arrangement method of a semiconductor memory is provided, which is capable of securing a stable operation by preventing data loss of a memory cell through sub-bias stabilization of a CSN driving part and a DRAM cell. CONSTITUTION: A semiconductor memory includes a plurality of memory cell arrays consisting of plural memory cells. A bit line sense amp array is shared by adjacent memory cell arrays in one direction. A sub-word line driver array is shared by an adjacent memory cell array to the one direction and has a region overlapped with the bit line sense amp array and crossed vertically. The bit line sense amp array and the sub-word line driver array include VBB and VPP biases arranged in a length direction, respectively.