| 摘要 |
PROBLEM TO BE SOLVED: To provide a counter circuit that can reduce the power consumption while maintaining the operating frequency equal to that of a conventional synchronous counter. SOLUTION: The counter circuit 100 comprises a synchronous counter section 110, an asynchronous counter section 120, and a synchronization circuit section 130k. The synchronization circuit section 130k comprises a latch means 140 and a clear control signal generating circuit 150k. The latch means 140 uses a clear preparation signal outputted from the asynchronous counter section 120 to latch a frequency division signal 103 outputted from the synchronous counter section 110. The clear control signal generating circuit 150k comprises a count section 160k and a second logic circuit 170 and outputs a clear control signal 106 at a clock cycle at which the count of the counter circuit 100 reaches a prescribed second count by receiving an output signal 105 of the latch means 140 and a clock signal 101.
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