发明名称 METHOD AND CIRCUIT FOR CONTROLLING OUTPUT BUFFER TO BUS SIGNAL LINE
摘要 PROBLEM TO BE SOLVED: To provide a method and circuit for controlling an output buffer to a bus signal line in a package circuit so as to reduce production of ground noise and to decrease the power consumption. SOLUTION: A control signal source validating an output buffer is given to flip-flop circuits 41 to 44, which produce a plurality of kinds of control signals with different timings. An n-bit bus data output buffer is classified into four groups, and control signals #1 to #4 outputted from the flip-flop circuits 41 to 44 are fed to output buffers 11 to 14 by each group with distribution. Controlling an application timing of the control signals to n-sets of the output buffers in time division and dividing the simultaneous operating signal can decrease number of simultaneous operating signals and divide the simultaneous operating signal so as to decrease number of the simultaneous operating signals, occurrence of ground noise and reduce power consumption.
申请公布号 JP2003069408(A) 申请公布日期 2003.03.07
申请号 JP20010253322 申请日期 2001.08.23
申请人 FUJITSU ACCESS LTD 发明人 AIHARA TAKESHI;HASHIMOTO TAKASHI
分类号 G06F3/00;H03K19/003;H03K19/0175;H04L25/02;(IPC1-7):H03K19/003;H03K19/017 主分类号 G06F3/00
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