METHOD FOR FINDING NOISE AT OUTPUT BY SIMULATING NOISE AT INPUT OF STATIC GATE

摘要

PROBLEM TO BE SOLVED: To provide a means for avoiding a trouble of a noise in designing an integrated circuit easily. SOLUTION: The present invention is a method to find a noise at the output of a static logic gate by simulating a noise at the input of the static logic gate. This method identifies PFET and NFET used when driving the input of the static gate by a particular voltage pattern. When an FET is identified, a P/N ratio is calculated for every possible input combination. The maximum P/N ratio or the minimum P/N ratio is selected and a noise signal at the input of the gate can be simulated. The signal arising at the output of the gate is a noise which can be used to evaluate other circuits as to noise problems. By using the noise created in this method, a designer of an integrated circuit is able to create a computer simulation which makes an electrical environment where an integrated circuit operates into a model in a satisfactory manner.