| 摘要 |
PROBLEM TO BE SOLVED: To provide a high-speed communication controller allowing transfer in a maximum bus width even if inconsistency of data alignment occurs when DMA- transferring a communication frame to separate areas, i.e. a header part and a data part. SOLUTION: In this data transfer device, an aligner ALIGN is provided halfway along a bus connecting a DMA controller and a storage means MAINMEM. The aligner ALIGN comprises a register RXREG storing data in the last writing; a selector RXSEL selecting 32 bits from a value in the data from the DMAC side and outputting the 32 bits to the bus on the storage area MAINMEM side; a register TXREG storing data in the last reading; a selector TXSEL selecting 32 bits from a value on the data bus from a CPU side and outputting the 32 bits to the DMAC side; an alignment inconsistency detection circuit ALIGN CHK selecting the inconsistency of the alignment and deciding a signal line selected by the selector; and an ADR CNV generating a CPU-side address signal from a DMAC-side address signal. Because the transfer in the maximum bus width is enable even if the inconsistency of the alignment occurs, the transfer can be executed in a half time and at the half number of times as compared to before.
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