| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory system in which deterioration of signal quality caused by signal reflection by mismatching of wiring impedance of a data bus is lightened, and which can perform read-out and write-in of data at high speed, in a memory system in which memory devices such as a DRAM or the like are branched for a data bus. SOLUTION: This system is memory device connected to a data bus, the memory device is provided with an active terminal circuit terminal-controlling this memory device and a control circuit controlling electrically this active terminal circuit to an active state or an inactive state, in it. Further, this memory system has a plurality of memory devices, while has a memory controller performing terminal control of the plurality of memory devices. In this case, also the memory controller is provided with the terminal circuit made an active state or an inactive state.
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