发明名称 METHOD FOR FORMING MULTILAYER WIRING
摘要 PROBLEM TO BE SOLVED: To reduce connection resistance and its irregularity in a method for forming a multilayer wiring. SOLUTION: After an interlayer insulating film 34 is formed which covers a lower wiring layer including an Al or Al alloy film 14b, a Ti film 14c for preventing nitriding, and a TiON film 14d for preventing reflection, a connection hole 34a is formed in the insulating film 34 by selective etching treatment using a resist layer as a mask. In this case, the bottom of the connection hole 34a is positioned not in the Ti film 14c as shown in (B) but in the TiON film 14d as shown in (A) After the resist layer is eliminated by O2 ashing, an upper wiring layer is formed which is continuous to the lower wiring layer via the connection hole 34a. In the case of the O2 ashing, deterioration of the state of interlayer connection caused by oxidation of the Ti film 14c can be prevented.
申请公布号 JP2003068849(A) 申请公布日期 2003.03.07
申请号 JP20020183059 申请日期 2002.06.24
申请人 YAMAHA CORP 发明人 YAMAHA TAKAHISA
分类号 H01L21/768;(IPC1-7):H01L21/768 主分类号 H01L21/768
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