发明名称 APPARATUS AND METHOD FOR TESTING PHASE LOCKED LOOP
摘要 PROBLEM TO BE SOLVED: To provide an apparatus and method for testing a phase locked loop (PLL) that can solve a task of conducting an enhanced test including verification and/or stop sequence of a frequency dynamic revision. SOLUTION: First a signal DT is set to '1', transistors P2, P3, N2 are used to isolate a phase comparator 11, a charge pump 12, a multiplexer (MUX) 15 and a lock detector 16 from a loop filter (LPF) 13 and a voltage-controlled oscillator (VCO) 14 and the formers are separately tested. Then the signal DT is set to '0', an output of an AND circuit 51 is given to the phase comparator 11 and the lock detector 16. Then the output frequency of the VCO 14 is measured corresponding to charging of the LPF 13, discharging of the LPF 13 and a steady-operation of the PLL.
申请公布号 JP2003069423(A) 申请公布日期 2003.03.07
申请号 JP20010253300 申请日期 2001.08.23
申请人 FUJITSU LTD 发明人 KWAME OSEI BOATENG
分类号 G01R31/316;G01R31/3167;G01R31/317;H03L7/08;H03L7/089;H03L7/095;H03L7/18 主分类号 G01R31/316
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