| 摘要 |
PROBLEM TO BE SOLVED: To provide a cache controller that suppresses peak current, permits normal operation even for a configuration using power wiring of usual wiring width, prevents the chip size from becoming larger, lessens production costs and permits high speed operation and a computer system having the cache controller. SOLUTION: The cache controller which exists in a layer between a CPU and main memory and controls cache memories (51-54) composed of a plurality of banks driven to and from active and non-active states independently of each other comprises a counting circuit 16, peak bank number setting means 17, 18 that sets the permissible maximum number of active banks (peak bank number), comparison circuit 19 that compares the number of banks in the active state and peak bank number and means for suppressing an access to a new bank when the number of banks in active state exceeds the peak bank number.
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