| 摘要 |
PROBLEM TO BE SOLVED: To provide a new processor system with a peripheral function block whose devices respectively independently operate, having high operation speed and high CPU processing efficiency without increasing electric power consumption. SOLUTION: This processor system 1 wherein a CPU 11 and the plurality of devices P1-Pn constituting the peripheral block 3 of the CPU 11 exchange a signal via a first bus (MBUS) 14 is provided with a second bus (PCBUS30) for exchanging a signal among the plurality of devices P1-Pn. The respective devices P1-Pn are provided with a connection/separation means gate circuits P1g-Png connectable/separable to/from the second bus 30. A signal changeover means (SMX) 24 having a plurality of connection means changing over the signals transmitted through a plurality of signal lines and selecting the device P1-Pn of a connection destination is provided between an output signal bus (PCBUS) 31 and an input signal bus (PCBUS) 32 constituting the second bus 30.
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