发明名称 CONNECTION PAD ARRANGEMENT FOR ELECTRONIC CIRCUIT COMPRISING FUNCTIONAL LOGIC CIRCUIT AND FLASH EEPROM
摘要 PROBLEM TO BE SOLVED: To provide an integrated circuit (IC1) comprising a functional logic circuit (1) and flash EEPROM (2), which are connected to a pad arrangement (PAD) via mixing devices (IMUX and OMUX). SOLUTION: The pad arrangement (PAD) comprises two connection pads (CP1 and CP2), and the good 'bondability' of the pad is assured by probing work for two times at most in the respective connection pads. This is particularly useful in the present case of combined functional logic and flash EEPROM, where three probings are generally required for the flash test of EEPROM, the digital test of the functional logic circuit and the analog test of the circuit. In a preferred embodiment, the integrated circuit (IC2) comprises a first set of dedicated connection pads coupled to the functional logic circuit (1) and a distinct second set of dedicated connection pads coupled to flash EEPROM (2).
申请公布号 JP2003068811(A) 申请公布日期 2003.03.07
申请号 JP20020001038 申请日期 2002.01.08
申请人 ALCATEL 发明人 SCHMIT JEAN-JACQUES;OP T EYNDE FRANK NICO LIEVEN;OCTAVE CHARLIER VINCENT JEAN-M
分类号 H01L21/66;G11C29/48;H01L27/115;(IPC1-7):H01L21/66 主分类号 H01L21/66
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