发明名称 |
Memory device and method having data path with multiple prefetch I/O configurations |
摘要 |
A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals. |
申请公布号 |
US2003043658(A1) |
申请公布日期 |
2003.03.06 |
申请号 |
US20020278509 |
申请日期 |
2002.10.22 |
申请人 |
KEETH BRENT;JOHNSON BRIAN;MANNING TROY A. |
发明人 |
KEETH BRENT;JOHNSON BRIAN;MANNING TROY A. |
分类号 |
G11C11/409;G11C7/10;G11C11/407;G11C11/4096;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/409 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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