Circuit device for logic gate, has series connection of n-MOS and p-MOS transistors with gates joined and supplied with clock signal, inverse clock being fed to spare terminal of n-MOS transistor

摘要

The circuit device has an n-MOS (501) transistor connected in series with a p-MOS transistor (502) the gates of the two MOSFETs (501a, 502a) being connected together and to a clock signal (NOT phi h). The free electrode (drain or source) of the p-MOS transistor is connected to a reference voltage, e.g. Vdd and the free electrode of the n-MOS device is connected to a non-inverted version of the clock signal ( phi h). The output (504), the current flow across the being transistors controlled in dependence on the signal supplied to the control terminals. An Independent claim for a logic gate is also included.