发明名称 |
Semiconductor integrated circuit device, method of testing the same, database for design of the same and method of designing the same |
摘要 |
Elements of a combinational circuit are divided into plural groups. The output from a terminal Q is fixed at shifted timing in flip-flop circuits belonging to each of groups X, Y and Z resulting from this grouping. With the outputs from the terminals Q of the flip-flop circuits thus fixed, an operation of a shift mode is carried out. When the operation of the shift mode is completed, a hold releasing operation and a capture operation are carried out with respect to each of the groups of the flip-flop circuits. For example, the hold releasing operation is carried out when one clock is at a high level with the capture operation carried out when the clock is at a low level, or the hold releasing operation is successively carried out with respect to each of the groups and then the capture operation for capturing a data signal is carried out with respect to each of the groups.
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申请公布号 |
US2003046643(A1) |
申请公布日期 |
2003.03.06 |
申请号 |
US20020281230 |
申请日期 |
2002.10.28 |
申请人 |
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发明人 |
OHTA MITSUYASU;TAKEOKA SADAMI |
分类号 |
G01R31/28;G01R31/3185;G06F11/22;G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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