发明名称 |
Unified design parameter dependency management method and apparatus |
摘要 |
Managing signal parameters in a logic design typically includes defining a signal parameter with a value, maintaining the defined signal parameter in a central database, and using the defined signal parameter that is maintained in the central database in computer code for a logic design.
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申请公布号 |
US2003046051(A1) |
申请公布日期 |
2003.03.06 |
申请号 |
US20010994574 |
申请日期 |
2001.11.26 |
申请人 |
WHEELER WILLIAM R.;ADILETTA MATTHEW J.;FENNELL TIMOTHY J. |
发明人 |
WHEELER WILLIAM R.;ADILETTA MATTHEW J.;FENNELL TIMOTHY J. |
分类号 |
G06F17/50;(IPC1-7):G06F7/60 |
主分类号 |
G06F17/50 |
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代理人 |
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主权项 |
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地址 |
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