| 摘要 |
A processing system allows direct data downloads from a non-volatile memory to a volatile memory. During a power-up operation, the volatile memory requests a direct transfer of data from the non-volatile memory. Bypassing a communication bus to a processor, the direct transfer allows for a faster transfer to the volatile memory. Power and capacitive bus loading are also reduced. Once the volatile memory is loaded, a system reset signal is provided from the volatile memory to indicate that the memory is ready.
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